High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

Author

Ishii, Kiyoshi ; Ichino, Haruhiko ; Kobayashi, Yoshiji ; Yamaguchi, Chikara

Author_Institution

Integrated Circuit Technol. Lab., NTT LSI Labs., Kanagawa, Japan

Volume

29

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

546

Lastpage

550

Abstract

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-μm photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV_p-p. An extremely high input sensitivity of 15 mV_p-p and a wide phase margin of 260° at 10 Gb/s are achieved

Keywords

bipolar integrated circuits; digital communication systems; digital integrated circuits; elemental semiconductors; optical receivers; silicon; 0.5 micron; 15 Gbit/s; 31 GHz; SST-1C transistors; Si; Si bipolar technology; decision circuit; high-bit-rate; high-input-sensitivity; optical fibre communication; photolithography; super self-aligned process; wide-band preamplifier; Circuit synthesis; Cutoff frequency; Design optimization; Lithography; Optical design; Optical fiber communication; Preamplifiers; Transistors; Voltage; Wideband;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.284706

Filename

284706