AsAP: An Asynchronous Array of Simple Processors

Author

Yu, Zhiyi ; Meeuwsen, Michael J. ; Apperson, RyanW ; Sattari, Omar ; Lai, Michael ; Webb, JeremyW ; Work, Eric W. ; Truong, Dean ; Mohsenin, Tinoosh ; Baas, Bevan M.

Volume

43

Issue

3

fYear

2008

fDate

3/1/2008 12:00:00 AM

Firstpage

695

Lastpage

705

Abstract

An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.

Keywords

CMOS digital integrated circuits; digital signal processing chips; integrated circuit design; multiprocessing systems; parallel architectures; parallel processing; AsAP; CMOS process; DSP; IEEE 802.11 a-g; JPEG encoder core; MIMD; asynchronous array; asynchronously clocked independent processors; chip multiprocessor; digital signal processing; frequency 116 MHz; frequency 475 MHz; power 2.4 mW; processors dissipation; programmable processors; size 0.18 mum; voltage 0.9 V; voltage 1.8 V; voltage 2.0 V; wireless LAN baseband transmitter; Circuits; Clocks; Computer architecture; Costs; Digital signal processing; Digital signal processing chips; Energy efficiency; Fabrication; High performance computing; Throughput; Array processor; DSP; GALS; MIMD; chip multi-processor; digital signal processing; globally asynchronous locally synchronous; many-core; multi-core;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.916616

Filename

4456790