• DocumentCode
    1081891
  • Title

    Formal verification of statecharts using finite-state model checkers

  • Author

    Zhao, Qianchuan ; Krogh, Bruce H.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
  • Volume
    14
  • Issue
    5
  • fYear
    2006
  • Firstpage
    943
  • Lastpage
    950
  • Abstract
    This brief concerns the formal verification of properties of statecharts, a hierarchical state machine formalism for designing control-system logic. Various semantics have been defined for statecharts in terms of the microsteps that determine the transitions between statechart configurations. We show how computation tree logic (CTL) specifications for a statechart can be verified using a finite-state model checker such as SMV. The inputs to the model checker are a model and an associated expansion of the CTL formula that reflect the semantics. A Kripke structure with marked states provides the formal relationship between the expanded model and the original statechart structure and CTL specification. The results apply to a general class of semantics and statecharts with bounded behaviors. The approach is illustrated with a small example
  • Keywords
    control system synthesis; discrete systems; finite state machines; formal logic; formal verification; computation tree logic specifications; control-system logic design; discrete control; finite-state model checker; formal verification; hierarchical state machine formalism; statechart configurations; Algorithm design and analysis; Computer errors; Control systems; Councils; Digital circuits; Formal verification; Logic design; Protocols; Scholarships; Software tools; Control logic; discrete control; formal verification; statecharts;
  • fLanguage
    English
  • Journal_Title
    Control Systems Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-6536
  • Type

    jour

  • DOI
    10.1109/TCST.2006.876921
  • Filename
    1668157