DocumentCode :
1082010
Title :
A CMOS Resizing Methodology for Analog Circuits
Author :
Levi, Timotheé ; Tomas, Jean ; Lewis, Noélle ; Fouillat, Pascal
Author_Institution :
LIMMS, Univ. of Tokyo, Tokyo
Volume :
26
Issue :
1
fYear :
2009
Firstpage :
78
Lastpage :
87
Abstract :
This article presents a CMOS resizing methodology for analog circuits during a technology migration, with easy-to-apply scaling rules based on a simple MOS transistor model. The goals are to transpose a circuit topology from one technology to another while preserving the main figures of merit and to quickly calculate the new transistor dimensions.
Keywords :
CMOS analogue integrated circuits; MOSFET; integrated circuit design; network topology; scaling circuits; CMOS resizing methodology; MOS transistor model; analog circuit; circuit topology; scaling rule; transistor dimension; Analog circuits; CMOS analog integrated circuits; CMOS technology; Circuit optimization; Circuit testing; Energy consumption; Equations; MOSFET circuits; Operational amplifiers; Transconductance; MOS technology; analog design; design reuse; resizing methodology; technology migration;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2009.1
Filename :
4760119
Link To Document :
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