DocumentCode :
1082068
Title :
A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)]
Author :
Davidson, Scott
Author_Institution :
Sun Microsystems
Volume :
26
Issue :
1
fYear :
2009
Firstpage :
98
Lastpage :
101
Abstract :
This is a review of System on Chip Test Architectures: Nanometer Design for Testability (edited by Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba). Overall, this is a good guide to the frontiers of test. For most of the chapters, the selection of subjects and the detail level is just right, largely because this book is a follow-on to a more introductory book, VLSI Test Principles and Architectures. If one of the more basic books on testing is not adequate for your requirements, this text would make a nice addition to your library. It would also do well as a text in an advanced graduate course.
Keywords :
Automatic testing; Books; Design for testability; Logic testing; Micromechanical devices; Network-on-a-chip; Sections; Sun; System testing; System-on-a-chip; DFT; FPGA; MEMS; SiP; SoC; TAM; nanotechnologies; random access scan; test architecture;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2009.2
Filename :
4760123
Link To Document :
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