DocumentCode :
1082382
Title :
Module orientation algorithm using reconstruction of nets and mean field annealing
Author :
Kim, S.S. ; Kyung, C.M.
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Volume :
27
Issue :
13
fYear :
1991
fDate :
6/20/1991 12:00:00 AM
Firstpage :
1198
Lastpage :
1200
Abstract :
A new module orientation algorithm using mean field annealing for minimising the half-perimeter routing length of all the nets in a circuit based on a multipin net model is presented. Experimental results on some example circuits have shown 13 to 24% reductions of half-perimeter routing length compared to the initial module orientation which was arbitrarily given.
Keywords :
VLSI; circuit layout CAD; integrated circuit technology; simulated annealing; VLSI layout; half-perimeter routing length; mean field annealing; module orientation algorithm; multipin net model; nets reconstruction; placement;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19910746
Filename :
132748
Link To Document :
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