DocumentCode
108239
Title
Employing Symmetric Dual-Rail Logic to Thwart LPA Attack
Author
Nian-Hao Zhu ; Yu-Jie Zhou ; Hong-Ming Liu
Author_Institution
Dept. of Electron. Eng., Shanghai Jiao Tong Univ., Shanghai, China
Volume
5
Issue
4
fYear
2013
fDate
Dec. 2013
Firstpage
61
Lastpage
64
Abstract
Leakage power analysis (LPA) attacks aim at finding the secret key of a cryptographic device from measurements of its static (leakage) power. This novel power analysis attacks take advantage of the dependence of the leakage power of CMOS integrated circuits on the data they process. This letter proposes symmetric dual-rail logic (SDRL), a standard cell LPA attack countermeasure that theoretically resists the LPA attacks. The technique combines standard building blocks to make new compound standard cells, which have a close to constant leakage power consumption. Experiment results show SDRL is a promising approach to implement a LPA-resistant crypto processor.
Keywords
CMOS integrated circuits; CMOS logic circuits; cryptography; logic gates; CMOS integrated circuits; CMOS logic gates; LPA-resistant crypto processor; SDRL; constant leakage power consumption; cryptographic device; leakage power analysis attacks; secret key; static power; symmetric dual-rail logic; thwart LPA attack; two-input NAND gate; CMOS integrated circuits; Correlation coefficient; Cryptography; Field programmable gate arrays; Leakage currents; Logic gates; Correlation power analysis; cryptography; differential power analysis; leakage power analysis; power analysis; simple power analysis;
fLanguage
English
Journal_Title
Embedded Systems Letters, IEEE
Publisher
ieee
ISSN
1943-0663
Type
jour
DOI
10.1109/LES.2013.2279918
Filename
6588595
Link To Document