Title :
Capacitance calculations in MOSFET VLSI
Author_Institution :
Burroughs Corporation, San Diego, CA, USA
fDate :
1/1/1982 12:00:00 AM
Abstract :
A simple empirical relation for the calculation of the capacitance of interconnection lines in MOSFET VLSI, including edge effects, is presented. The equation gives approximate results compared to two-dimensional computer calculations.
Keywords :
Annealing; Capacitance; Conductive films; Conductors; Electrons; Gallium arsenide; MOSFET circuits; Oxidation; Silicon; Very large scale integration;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1982.25454
