A low-voltage, low-power CMOS delay element

Author

Kim, Gyudong ; Kim, Min-Kyu ; Chang, Byoung-Soo ; Kim, Wonchan

Author_Institution

Dept. of Electron. Eng., Seoul Nat. Univ., South Korea

Volume

31

Issue

7

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

966

Lastpage

971

Abstract

A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 μm CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed

Keywords

CMOS digital integrated circuits; MOS-controlled thyristors; compensation; delay circuits; jitter; 0.8 micron; 1 V; 2.6 to 76.3 ns; CMOS thyristor; LV CMOS delay element; jitter performance; low-power CMOS delay element; noisy environment; temperature compensation; CMOS technology; Delay; Inverters; Jitter; Low voltage; MOS devices; MOSFETs; Temperature sensors; Threshold voltage; Thyristors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508210

Filename

508210