Title :
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor
Author :
Murabayashi, Fumio ; Yamauchi, Tatsumi ; Yamada, Hiromichi ; Nishiyama, Takahiro ; Shimamura, Kotaro ; Tanaka, Shigeya ; Hotta, Takashi ; Shimizu, Teruhisa ; Sawamoto, Hideo
Author_Institution :
Process. Dev. Center, Hitachi Ltd., Kanagawa, Japan
fDate :
7/1/1996 12:00:00 AM
Abstract :
Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 μm CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS
Keywords :
CMOS digital integrated circuits; VLSI; buffer circuits; floating point arithmetic; integrated circuit noise; microprocessor chips; reduced instruction set computing; 0.3 micron; 2.5 V; 200 MHz; 350 mW; 400 MFLOPS; CMOS circuit techniques; floating point macrocell; high noise immunity; high speed operation; leakless buffer circuit; low power dissipation; noise tolerant precharge circuit; superscalar RISC processor; CMOS process; CMOS technology; Circuit noise; Delay; MOS devices; Macrocell networks; Power dissipation; Power supplies; Reduced instruction set computing; Registers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
