DocumentCode
1082996
Title
Speed limitations due to interconnect time constants in VLSI integrated circuits
Author
Sinha, A.K. ; Cooper, J.A., Jr. ; Levinstein, H.J.
Author_Institution
Bell Laboratories, Murray Hill, NJ
Volume
3
Issue
4
fYear
1982
fDate
4/1/1982 12:00:00 AM
Firstpage
90
Lastpage
92
Abstract
The RC time constants for various interconnect materials, including poly-Si, silicides, and Al, are compared with MOSFET speeds at near-micron and submicron design rules. It is found that for design rules below ∼ 2 µm, the rise time of Al interconnects one cm long can exceed the switching delay of state-of-the-art MOSFET circuits. This speed limitation becomes more severe as design rules are reduced further. The effects of the sheet resistance and thickness of gate level interconnects, the thickness of the field oxide, and the dielectric constant of the insulating overlays are quantified.
Keywords
Artificial intelligence; Delay effects; Dielectric constant; Integrated circuit interconnections; MOSFET circuits; Parasitic capacitance; Passivation; Silicides; Silicon compounds; Very large scale integration;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1982.25491
Filename
1482596
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