DocumentCode :
1082999
Title :
Parametric formulation of CMOS latch-up as a function of chip layout parameters
Author :
Lohia, Ramesh ; Ali, Akhtar
Author_Institution :
Rockwell Int., Newport Beach, CA, USA
Volume :
23
Issue :
1
fYear :
1988
Firstpage :
245
Lastpage :
250
Abstract :
The relationship between the CMOS latch-up characteristics and the chip layout parameters such as the location and spacing of the well and substrate tie-ups (straps) is studied. By measuring the strap current I/sub c/ at varying distances from the well-substrate boundary, it is found that placing these straps at the boundary is most effective. The holding current I/sub h/(x, N) at a point in the circuit is quantitatively related to (1) the distance of x of the well-substrate strap from this point, and (2) the doping level N of the respective region. An analytical expression of the form I/sub h/ (x, N)=e/sup a-b square root x/=I/sub oe//sup -b square root x/ is developed to predict the required frequency of strapping for a particular process technology, where coefficients a and b are functions of the doping. The impact of a strapping scheme on latch-up is explained in terms of a simple engineering model.<>
Keywords :
CMOS integrated circuits; semiconductor doping; CMOS latch-up; chip layout parameters; doping level; engineering model; holding current; process technology; strap current; straps; substrate tie-ups; well-substrate strap; CMOS technology; Circuits; Current measurement; Doping; Frequency; Pins; Semiconductor device measurement; Substrates; Testing; Topology;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.285
Filename :
285
Link To Document :
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