Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

Author

Kanan, Riad ; Hochet, Bertrand ; Declercq, Michel

Author_Institution

Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland

Volume

31

Issue

7

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

992

Lastpage

1000

Abstract

This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FET´s only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 μm MESFET process. The power consumption of an inverter is about 10 μW at 100 MHz

Keywords

III-V semiconductors; MESFET integrated circuits; field effect logic circuits; gallium arsenide; integrated circuit noise; logic design; 0.6 micron; 10 muW; 100 to 500 MHz; GaAs; MESFET process; complementary logic signals; complex gates; enhancement-mode FET; frequency divider; inverter chain; low-power logic family; noise margins; nonratioed logic; power consumption; process variations immunity; pseudo-complementary FET logic; ring oscillator; static logic family; CMOS logic circuits; Clocks; Energy consumption; FETs; Gallium arsenide; Logic design; Pulse inverters; Signal generators; Silicon; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508213

Filename

508213