Title :
Offset-trimming bit-line sensing scheme for gigabit-scale DRAM´s
Author :
Jung-Won Sub ; Rho, Kwang-Myoung ; Park, Chan-Kwang ; Koh, Yo-Hwan
Author_Institution :
Memory R&D Div., Hyundai Electron. Ind. Co. Ltd., Kyoungji, South Korea
fDate :
7/1/1996 12:00:00 AM
Abstract :
A new offset-trimming bit-line sensing scheme is described which is suitable for gigabit-scale DRAM´s. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimming time is analyzed and verified with simulation results. As compared with a conventional direct sensing scheme, the proposed scheme shows remarkable improvement on the sensitivity. A test device was fabricated with a 0.25 μm CMOS technology and its measurement results indicate the successful operation of offset-trimming
Keywords :
CMOS memory circuits; DRAM chips; 0.25 micron; CMOS technology; deep submicron transistors; dynamic RAM; effective offset voltage dependence; gigabit-scale DRAM; offset-trimming bit-line sensing scheme; sensitivity degradation suppression; Analytical models; CMOS technology; Circuits; Degradation; Feedback; Inverters; MOSFETs; Random access memory; Timing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
