A high resolution frequency multiplier for clock signal generation

Author

Fried, Rafael ; Rosin, Eyal

Author_Institution

Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland

Volume

31

Issue

7

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

1059

Lastpage

1062

Abstract

This paper presents a high resolution frequency multiplier (FMUL) with the ability to multiply frequency with a programmable high multiplication factor, in the order of 10²-10⁴ and of the form N/M. It was designed for chip-sets that use a real time clock (32768 Hz) for power-save operation, and an additional high-frequency oscillator, in the range of 40-60 MHz, for regular operation. Using the FMUL spares the need for the additional high-frequency oscillator. The FMUL´s frequency resolution is 100 ppm, and its jitter is less than 200 ps. The circuit is designed to work with 25 V supply voltage. It is implemented in a standard 0.8 pm N-well CMOS process, and its area is 0.48 mm²

Keywords

CMOS integrated circuits; clocks; frequency multipliers; jitter; pulse generators; real-time systems; 0.8 micron; 2 to 5 V; 32768 Hz; N-well CMOS process; clock signal generation; frequency resolution; high resolution frequency multiplier; jitter; power-save operation; programmable high multiplication factor; real time clock; Circuits; Clocks; Digital control; Frequency; Oscillators; Phase locked loops; Signal generators; Signal resolution; Tuning; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508222

Filename

508222