DocumentCode
1083157
Title
A multiplier-accumulator macro for a 45 MIPS embedded RISC processor
Author
Murakami, Hiroalti ; Yano, Na oka ; Ootaguro, Yukio ; Sugeno, Yukio ; Ueno, Maki ; Muroya, Yukinori ; Aramaki, Tsuneo
Author_Institution
Microelectron. Eng. Lab., Toshiba Corp., Kawasaki, Japan
Volume
31
Issue
7
fYear
1996
fDate
7/1/1996 12:00:00 AM
Firstpage
1067
Lastpage
1071
Abstract
This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth´s encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication followed by 64 b addition) per cycle at 56.5 MHz. The area is 2.35 mm2 with 0.4 μm CMOS technology
Keywords
CMOS logic circuits; adders; microprocessor chips; multiplying circuits; real-time systems; reduced instruction set computing; 0.4 micron; 32 bit; 45 MIPS; 56.5 MHz; 64 bit; Booth´s encoder; CMOS technology; embedded RISC processor; full adder array; multiplier-accumulator macro; multiply-add operation; Algorithm design and analysis; CMOS technology; Costs; Delay; Engines; Flip-flops; Information systems; Microelectronics; Reduced instruction set computing; Throughput;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.508224
Filename
508224
Link To Document