Title :
A novel high-speed silicon bipolar transistor utilizing SEG and CLSEG
Author :
Siekkinen, J.W. ; Neudeck, G.W. ; Glenn, J.L. ; Venkatesan, S.
Author_Institution :
Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
5/1/1994 12:00:00 AM
Abstract :
The concept and fabrication results are presented for a novel high-speed silicon bipolar transistor structure using selective epitaxy (SEG) and confined lateral growth (CLSEG) to form a double self-aligned single crystal contacted device. It provides significant improvements in the parasitics Ccb and Ccs, and in the ECL gate delay
Keywords :
bipolar transistors; elemental semiconductors; epitaxial growth; semiconductor growth; silicon; ECL gate delay improvement; Si; confined lateral growth; double self-aligned single crystal contacted device; fabrication; high-speed bipolar transistor; parasitics improvement; selective epitaxy; Bipolar transistors; Circuits; Delay; Epitaxial growth; Etching; Fabrication; Geometry; Implants; Parasitic capacitance; Silicon;
Journal_Title :
Electron Devices, IEEE Transactions on
