Leading-zero anticipatory logic for high-speed floating point addition

Author

Suzuki, Hiroaki ; Morinaka, Hiroyuki ; Makino, Hiroshi ; Nakase, Yasunobu ; Mashiko, Koichiro ; Sumi, Tadashi

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

31

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

1157

Lastpage

1164

Abstract

This paper describes a new leading-zero anticipatory (LZA) logic for high-speed floating-point addition (FADD). This logic carries out the pre-decoding for normalization concurrently with addition for the significand. It also performs the shift operation of normalization in parallel with the rounding operation. The use of simple Boolean algebra allows the proposed logic to be constructed from a simple CMOS circuit. Its area penalty is as small as 30% of the conventional LZA method. The FADD core using the proposed logic was fabricated by 0.5 μm CMOS technology with triple metal interconnections and runs at 164 MHz under the condition of V_DD=3.3 V

Keywords

Boolean algebra; CMOS logic circuits; floating point arithmetic; 0.5 micron; 164 MHz; 3.3 V; Boolean algebra; CMOS circuit; FADD core; LZA logic; area penalty; high-speed floating point addition; leading-zero anticipatory logic; normalization; pre-decoding; rounding operation; shift operation; triple metal interconnections; Boolean algebra; CMOS logic circuits; CMOS technology; Delay effects; Floating-point arithmetic; Graphics; Integrated circuit interconnections; Logic circuits; Logic functions; Visualization;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508263

Filename

508263