A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

Author

Chen, Dao-Long

Author_Institution

Symbios Logic Inc., Fort Collins, CO, USA

Volume

31

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

1170

Lastpage

1176

Abstract

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s

Keywords

CMOS digital integrated circuits; clocks; data communication; digital phase locked loops; jitter; phase locked loops; 0.8 micron; 125 Mbit/s; 280 Mbit/s; 45 mW; 5 V; 92 mW; analog PLL; area efficiency; clock circuit; data communications; data recovery circuit; digital PLL; high-speed serial interface; jitter; power efficiency; single-polysilicon double-metal CMOS process; CMOS process; Circuits; Clocks; Data communication; Energy consumption; Jitter; Phase locked loops; Power generation; Signal design; Signal generators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508265

Filename

508265