DocumentCode :
1083681
Title :
Fully ion implanted InP junction FET´s
Author :
Boos, J.B. ; Dietrich, H.B. ; Weng, T.H. ; Sleger, K.J. ; Binari, S.C. ; Henry, R.L.
Author_Institution :
Naval Research Laboratory, Washington, DC
Volume :
3
Issue :
9
fYear :
1982
fDate :
9/1/1982 12:00:00 AM
Firstpage :
256
Lastpage :
258
Abstract :
This article reports on the fabrication and performance of all ion implanted, 1.0 µm gate length, InP junction field-effect transistors (JFET\´s). Device fabrication includes the use of multiple energy Si implantation, selective Be implantation, proximity annealing, and Cl2 plasma etching. The observed 25 V gate-source breakdown voltage is shown, by 
and SIMS analysis, to be a result of a linearly graded junction. At 4 GHz, the maximum insertion gain for these devices was 9.7 dB, while tuning for the optimum noise performance yielded a noise figure of 4.9 dB with an associated gain of 5.8 dB. These results encourage the development of a planar InP JFET technology for use in logic, microwave power, and optoelectronic applications.
and SIMS analysis, to be a result of a linearly graded junction. At 4 GHz, the maximum insertion gain for these devices was 9.7 dB, while tuning for the optimum noise performance yielded a noise figure of 4.9 dB with an associated gain of 5.8 dB. These results encourage the development of a planar InP JFET technology for use in logic, microwave power, and optoelectronic applications.Keywords :
Annealing; Capacitance-voltage characteristics; Etching; FETs; Fabrication; Indium phosphide; Noise figure; Performance gain; Plasma applications; Plasma devices;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/EDL.1982.25559
Filename :
1482664
Link To Document :
