• DocumentCode
    1083781
  • Title

    Halo and LDD Engineering for Multiple VTH High Performance Analog CMOS Devices

  • Author

    Guo, Jyh-Chyurn

  • Author_Institution
    Nat. Chiao-Tung Univ., Hsinchu
  • Volume
    20
  • Issue
    3
  • fYear
    2007
  • Firstpage
    313
  • Lastpage
    322
  • Abstract
    High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-mum logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.
  • Keywords
    CMOS analogue integrated circuits; aggressive gate oxide thickness scaling; dual gate oxide module; high performance analog CMOS devices; lightly doped drain engineering; logic-based mixed-signal CMOS process; size 0.13 mum; threshold voltages; CMOS logic circuits; CMOS process; Degradation; Helium; Human computer interaction; Implants; Logic devices; Power engineering and energy; Reliability engineering; Threshold voltage; Dual gate oxide; LDD engineering; halo; high performance analog (HPA); multiple threshold voltages;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2007.901408
  • Filename
    4285826
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1083781