Scarce-state-transition syndrome-former error-trellis decoding of (n,n-1) convolutional codes

Author

Lee, L. H Charles ; Tait, David J. ; Farrell, Patrick G.

Author_Institution

Sch. of Math., Phys. Comput. & Electron., Macquarie Univ., Sydney, NSW, Australia

Volume

44

Issue

1

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

7

Lastpage

9

Abstract

A novel scarce-state-transition (SST) type trellis decoding system for (n,n-1) convolutional codes with coherent BPSK signals is proposed. The new system retains the same number of binary comparisons as the syndrome-former trellis decoding technique. Like the original SST-type encoder trellis technique, the proposed system is also suitable for CMOS VLSI implementation. A combination of the two techniques results in a less complex and low power consumption decoding system

Keywords

CMOS digital integrated circuits; VLSI; Viterbi decoding; convolutional codes; phase shift keying; CMOS VLSI; binary comparisons; coherent BPSK signals; convolutional codes; low power consumption decoding system; scarce state transition; syndrome-former error-trellis decoding; trellis decoding system; Australia; Binary phase shift keying; Bit error rate; Convolutional codes; Energy consumption; Information rates; Maximum likelihood decoding; Power measurement; Very large scale integration; Viterbi algorithm;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.476087

Filename

476087