• DocumentCode
    1084627
  • Title

    Latchup-free Schottky-barrier CMOS

  • Author

    Sugino, Michael ; Akers, Lex A. ; Rebeschini, Michael E.

  • Author_Institution
    Semiconductor Research Development Laboratory, Motorola, Phoenix, AZ
  • Volume
    30
  • Issue
    2
  • fYear
    1983
  • fDate
    2/1/1983 12:00:00 AM
  • Firstpage
    110
  • Lastpage
    118
  • Abstract
    A common failure mechanism in bulk CMOS integrated circuits is due to the latchup of the parasitic SCR structure. Using Schottky-barrier junctions for the source and drain of the p-channel transistors eliminates the p-n-p-n structure. A technology utilizing platinum-silicide p-channel source and drain and ion-implanted n-channel source and drain was realized demonstrating latchup resistance without many sacrifices inherent with other methods. Anomalies in the p-MOSFET characteristics are reported and discussed.
  • Keywords
    CMOS technology; Circuits; Contact resistance; Electrons; Energy states; Silicon on insulator technology; Substrates; Thyristors; Very large scale integration; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1983.21083
  • Filename
    1482984