A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

Author

Yeh, Chih-Chieh ; Wang, Tahui ; Tsai, Wen-Jer ; Lu, Tao-Cheng ; Liao, Yi-Ying ; Chen, Hung-Yueh ; Zous, Nian-Kai ; Ting, WenChi ; Ku, Joseph ; Lu, Chih-Yuan

Author_Institution

Macronix Int. Co. Ltd., Hsinchu, Taiwan

Volume

25

Issue

9

fYear

2004

Firstpage

643

Lastpage

645

Abstract

The cause of over-erasure in a two-bit nitride storage flash memory cell is investigated. Extra positive charges accumulated above the n⁺ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V_t) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state V_t distribution, which will reduce overerasure significantly.

Keywords

flash memories; 2-bit flash memory cell; band-to-band hot hole; drain-induced barrier lowering effect; erase scheme; erase speed; n+ junction; nitride storage flash memory cell; nitride trapping storage; over-erased cell; overerasure suppression; positive charge; program-state distribution; source voltage; threshold voltage; Dielectrics; Electron traps; Flash memory; Flash memory cells; Hot carriers; MOSFETs; Nonvolatile memory; Threshold voltage; Tunneling; Voltage control; Band-to-band hot hole; Flash memory cell; nitride trapping storage; overerasure;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2004.833596

Filename

1327721