• DocumentCode
    1084718
  • Title

    A transient analysis of latchup in bulk CMOS

  • Author

    Troutman, Ronald R. ; Zappe, Hans P.

  • Author_Institution
    IBM, General Technology Division, Essex Junction, VT
  • Volume
    30
  • Issue
    2
  • fYear
    1983
  • fDate
    2/1/1983 12:00:00 AM
  • Firstpage
    170
  • Lastpage
    179
  • Abstract
    This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.
  • Keywords
    Bipolar transistors; CMOS integrated circuits; Capacitance; Diodes; Equivalent circuits; Helium; Latches; Semiconductor device modeling; Transient analysis; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1983.21091
  • Filename
    1482992
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1084718