Title :
A CMOS square-law vector summation circuit
Author :
Liu, Shen-Iuan ; Chang, Cheng-Chieh
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
7/1/1996 12:00:00 AM
Abstract :
A CMOS vector summation circuit using the square-law characteristics of MOS transistors in the saturation region is presented. Simulation and experimental results are given to verify the theoretical analyzes. Second-order effects such as mobility reduction and transistor mismatch are also investigated. The proposed circuits are expected to be useful in analog signal-processing applications
Keywords :
CMOS analogue integrated circuits; VLSI; analogue processing circuits; summing circuits; CMOS; analog signal-processing applications; mobility reduction; saturation region; second-order effects; square-law vector summation circuit; transistor mismatch; Analog circuits; Analytical models; CMOS technology; Circuit simulation; MOSFETs; Mirrors; Semiconductor device modeling; Threshold voltage; Transconductance; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
