Title :
Low-latency bit-parallel systolic VLSI implementation of FIR digital filters
Author :
Caraiscos, Christos G. ; Pekmestzi, Kiamal Z.
Author_Institution :
Dept. of Electron., Technological Educ. Inst. of Lamia, Greece
fDate :
7/1/1996 12:00:00 AM
Abstract :
A new scheme for a high-throughput and low-latency systolic implementation of FIR digital filters is proposed. The input and output sequences are in bit-parallel LSB-first bit-skewed form, and the throughput is limited by the propagation delay of a gated full adder and a latch. The bits of a full-bit output sample start coming out of the array three clock cycles after the bits of the corresponding input sample enter the array
Keywords :
FIR filters; VLSI; systolic arrays; FIR digital filter; VLSI systolic array; bit-parallel LSB-first bit-skewed sequences; gated full adder; latch; latency; propagation delay; throughput; Adders; Digital filters; Finite impulse response filter; Latches; Merging; Pipeline processing; Propagation delay; Systolic arrays; Throughput; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
