Low-latency bit-parallel systolic VLSI implementation of FIR digital filters

A new scheme for a high-throughput and low-latency systolic implementation of FIR digital filters is proposed. The input and output sequences are in bit-parallel LSB-first bit-skewed form, and the throughput is limited by the propagation delay of a gated full adder and a latch. The bits of a full-bit output sample start coming out of the array three clock cycles after the bits of the corresponding input sample enter the array