• DocumentCode
    1085055
  • Title

    Area-efficient self-calibration technique for pipe-lined algorithmic A/D converters

  • Author

    Nagaraj, K.

  • Author_Institution
    AT&T Bell Labs., Murray Hill, NJ, USA
  • Volume
    43
  • Issue
    7
  • fYear
    1996
  • fDate
    7/1/1996 12:00:00 AM
  • Firstpage
    540
  • Lastpage
    544
  • Abstract
    An area-efficient self-calibration technique for pipe-lined A/D converters is presented. It consists of trimming the reference voltage to each stage by means of a tunable MOSFET attenuator. This simplifies the calibration circuit in each stage and shifts most of the calibration task to a hardware that is shared by all stages
  • Keywords
    analogue-digital conversion; calibration; pipeline processing; area-efficient self-calibration; pipe-lined algorithmic A/D converter; reference voltage trimming; tunable MOSFET attenuator; Arithmetic; Attenuators; Calibration; Capacitors; Circuits; Clocks; Finite impulse response filter; Signal processing algorithms; Switches; Voltage;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.508433
  • Filename
    508433
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1085055