Noise analysis methodology for partially depleted SOI circuits

In partially depleted silicon-on-insulator (PD-SOI) technology, signal switching history and intial state of the circuit nodes can affect the device body voltage and also cause parasitic BJT leakage currents, which can lead to significant increase in noise propagation and noise failures. In this brief we explore the effects of input switching history, initial circuit conditions and the parasitic BJT device on all steps in a traditional noise analysis methodology: noise injection, noise propagation, and noise failure criterion. We present a new noise analysis methodology to account for the floating body and the BJT effects in PD SOI technology. We demonstrate the new technique on an industrial microprocessor design in PD SOI and show that the current noise analysis methods do not account for 56% of noise fails.