DocumentCode :
1085165
Title :
Annealed embeddings of communication patterns in an interconnection cached network
Author :
Gupta, Vipul ; Schenfeld, Eugen
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
Volume :
6
Issue :
11
fYear :
1995
fDate :
11/1/1995 12:00:00 AM
Firstpage :
1153
Lastpage :
1167
Abstract :
The communication needs of many parallel applications exhibit what we call switching locality. In such applications, each computation entity (process, thread, etc.) tends to restrict its communication to a small set of other entities. The physical location or proximity of these entities can be arbitrary, as long as the communication degree is small. The Interconnection Cached Network (ICN) is a reconfigurable network ideally suited for exploiting such locality. The use of fast small crossbar switches (Interconnection Caches) with a larger, but slower, reconfigurable network (optimized for connectivity) lets the ICN adapt to the communication requirements of individual applications, potentially achieving higher performance. Embedding communication patterns efficiently in an ICN, requires finding a bounded l-contraction of the underlying communication graph. The problem of identifying whether a graph has a bounded and l-contraction for a given integer l is known to be NP-complete for l>2. We describe a heuristic algorithm based on simulated annealing for this problem. We test the effectiveness of our approach by using it to embed graphs, representing regular communication patterns, for which the best solutions are deterministically known. The algorithm does not rely on any structural information of the communication pattern and is therefore applicable to irregular patterns as well. The results of applying our heuristics to embed such irregular graphs are also presented
Keywords :
cache storage; multiprocessor interconnection networks; optical interconnections; reconfigurable architectures; simulated annealing; ICN; communication graph; communication patterns; crossbar switches; interconnection cache; interconnection cached network; interconnection networks; latency reduction; optical networks; process mapping; reconfigurable network; reconfigurable parallel architectures; simulated annealing; switching locality; Centralized control; Communication switching; Computer applications; Delay; Intelligent networks; Lattices; Multiprocessor interconnection networks; Network topology; Simulated annealing; Switches;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/71.476187
Filename :
476187
Link To Document :
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