• DocumentCode
    1085409
  • Title

    Two-layer hierarchical matching method for energy-efficient CAM design

  • Author

    Chang, Y.-J.

  • Author_Institution
    Dept. of Comput. Sci., Nat. ChungHsing Univ., Taichung
  • Volume
    43
  • Issue
    2
  • fYear
    2007
  • Firstpage
    80
  • Lastpage
    82
  • Abstract
    An energy-efficient CAM design is introduced, in which both the match line capacitances and switching activities are minimised using a two-layer hierarchical matching method. The results measured from the fabricated chip show that, compared to the traditional NOR-type CAM, this design can deliver an energy reduction of 76% while improving the match performance by 29%
  • Keywords
    MOS memory circuits; NOR circuits; content-addressable storage; NOR-type CAM; energy reduction; energy-efficient CAM design; match line capacitances; two-layer hierarchical matching method;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20073406
  • Filename
    4084096
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1085409