Impact of polysilicon dry etching on 0.5 μm NMOS transistor performance: the presence of both plasma bombardment damage and plasma charging damage

Author

Gu, T. ; Okandan, M. ; Awadelkarim, O.O. ; Fonash, S.J. ; Rembetski, J.F. ; Aum, P. ; Chan, Y.D.

Author_Institution

Electron. Mater. & Processing Res. Lab., Pennsylvania State Univ., University Park, PA, USA

Volume

15

Issue

2

fYear

1994

Firstpage

48

Lastpage

50

Abstract

Two types of damage mechanisms resulting from polysilicon gate dry etching are identified in 0.5 μm NMOS transistors. One type of damage is found to be active even after full processing and to result in positive charge at the edge of the gate oxide. It is found to have no correlation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon antenna ratio as well as overetch percentage. This second type of damage is attributable to plasma charging.

Keywords

elemental semiconductors; insulated gate field effect transistors; semiconductor-insulator boundaries; silicon; sputter etching; 0.5 micron; NMOS transistor performance; Si; Si-SiO/sub 2/; antenna ratio; damage mechanisms; electrical stress; overetch percentage; passivation; plasma bombardment damage; plasma charging damage; polycrystalline Si; polysilicon dry etching; polysilicon gate; positive charge; submicron n-MOSFET; Degradation; Dry etching; FETs; MOS capacitors; MOSFETs; Plasma applications; Plasma chemistry; Plasma materials processing; Plasma sources; Stress;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.285377

Filename

285377