A new hardware realization of digital filters

A new approach to the implementation problem of digital filters is presented. This approach capitalizes on recent advances in semiconductor memory technology and is shown to offer significant reductions in cost and power consumption for the same speed of operation as that of existing realizations. Furthermore, this approach makes possible speeds of operation which cannot be achieved by existing realizations. The proposed approach yields a very flexible hardware configuration and a discussion of the various options is presented together with a comparison to existing realizations. The mean-squared error resulting from the use of finite word length is analyzed.