DocumentCode :
1086249
Title :
Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications
Author :
Sia, Choon Beng ; Ong, Beng Hwee ; Lim, Wei Meng ; Yeo, Kiat Seng ; Alam, Tariq
Author_Institution :
Cascade Microtech, Inc., Singapore
Volume :
55
Issue :
4
fYear :
2008
fDate :
4/1/2008 12:00:00 AM
Firstpage :
1058
Lastpage :
1066
Abstract :
A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.
Keywords :
inductors; radiofrequency integrated circuits; semiconductor device metallisation; silicon; RFIC applications; differential inductors; frequency 10 GHz; layout optimization; metallization; operating frequency; Conductors; Degradation; Inductance; Inductors; Metallization; Performance loss; Predictive models; Radio frequency; Radiofrequency integrated circuits; Silicon; Common mode rejection ratio (CMRR); differential; differential amplifier; ground-signal (GS); ground-signal-ground (GSG); ground-signal-signal-ground (GSSG); inductance; inductor; layout; mixed-mode $S$-parameter; mixed-mode $S$-parameter; optimization; quality factor;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2008.917536
Filename :
4459446
Link To Document :
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