• DocumentCode
    1086275
  • Title

    Smallest p-n-p-n memory cell

  • Author

    Tamama, Teruo ; Yamamoto, Yousuke ; Mizushima, Yoshihiko

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
  • Volume
    30
  • Issue
    8
  • fYear
    1983
  • fDate
    8/1/1983 12:00:00 AM
  • Firstpage
    927
  • Lastpage
    933
  • Abstract
    Although the p-n-p-n device is suitable for a 1-bit/cell static mamory, it has not yet been put to practical use because of its large cell size. By employing a sophisticated process involving single-crystal/poly-Si simultaneous growth on the same substrate, the smallest-sized vertical p-n-p-n device has been developed. Using this cell structure, a 12-bit scanner with 21.2-MHz transfer frequency, 16-µm pitch and 10-µmW/bit power dissipation has been fabricated. This cell structure is also applied to a static RAM with 22 × 27 = 594 µm2cell size. A high switching speed as well as a high packing density is predicted by this configuration.
  • Keywords
    Choppers; Frequency; Inverters; Power dissipation; Power semiconductor switches; Random access memory; Read-write memory; Semiconductor diodes; Substrates; Thyristors;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1983.21239
  • Filename
    1483140