DocumentCode
1086716
Title
10 Gbit/s low-power bit synchroniser with automatic retiming phase alignment
Author
Wennekers, P. ; Nowotny, U. ; Huelsmann, A. ; Kaufel, G. ; Koehler, Katrina ; Raynor, B. ; Schneider, Jurgen
Author_Institution
Fraunhofer-Inst. for Appl. Solid State Phys., Freiburg, Germany
Volume
27
Issue
17
fYear
1991
Firstpage
1529
Lastpage
1532
Abstract
A 10 Gbit/s bit-synchroniser circuit has been fabricated using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. The differential gain of the exclusive-or phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/+21 degrees relative to the ´in bit cell centre´ position of the negative going clock edge. The chip has a power dissipation of 160 mW when using a supply voltage of 1.90 V.
Keywords
integrated optoelectronics; optical communication equipment; synchronisation; 0.3 micron; 160 mW; AlGaAs-GaAs-AlGaAs; E/D process; automatic retiming phase alignment; differential gain; exclusive-or phase comparator circuit; low-power bit synchroniser; monotonous phase comparison; negative going clock edge; phase margins; power dissipation; quantum well FET process; recessed gate;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19910961
Filename
132789
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