Title :
Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow
Author :
Chung, Soonwan ; Tang, Zhenming ; Park, Seungbae
Author_Institution :
Mech. Eng. Dept., State Univ. of New York, Binghamton, NY
Abstract :
The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated
Keywords :
ball grid arrays; chip scale packaging; delamination; finite element analysis; flip-chip devices; fracture; integrated circuit interconnections; reflow soldering; solders; ball grid array package; board-level interconnect reflow; delamination; flip-chip chip-scale package; flip-chip interconnects; flip-chip solders; nonlinear finite-element analysis; phase change; solder bridging; solder packages; solder reflow; underfill fracture; Capacitive sensors; Chip scale packaging; Delamination; Fatigue; Lead; Semiconductor device modeling; Solids; Temperature; Tin; Volume measurement; Contact analysis; Pb-free solder; flip-chip; interfacial failure; phase change; reflow process; strain energy release rate; underfill fracture; volume expansion;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2006.890207