Title :
Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives
Author :
Sharifi, Hasan ; Choi, Tae-Young ; Mohammadi, Saeed
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN
Abstract :
This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved
Keywords :
CMOS integrated circuits; integrated circuit interconnections; microassembling; microwave receivers; mixed analog-digital integrated circuits; silicon; substrates; wafer level packaging; wafer scale integration; 0.18 micron; 10 GHz; CMOS technology; die-to-die interconnects; embedded passives; front-end receiver; heterogeneous integration; high-density interconnects; high-resistivity silicon substrate; input matching; microwave receiver; mixed-signal circuits; polymer wafer-level integration; radiofrequency circuits; system-on-chip; system-on-package; CMOS technology; Ceramics; Electronic packaging thermal management; Electronics packaging; Fabrication; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Radio frequency; Semiconductor device packaging; Heterogeneous integration; packaging; system- on-chip (SOC); system-on-package (SIP); wafer-scale integration;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2006.890221
