Comparisons of instabilities in scaled CMOS devices between plastic and hermetically encapsulated devices

Scaling down of transistor cell sizes causes some instabilities in CMOS devices under high temperature or high humidity bias stress, especially in plastic encapsulated devices. On CMOS test transistors with various kinds of the passivation layer, accelerated reliability tests have been conducted in this study. As a result of tests, it has been found that devices with a phosphosilicate glass passivation layer show remarkable threshold voltage shifts, which depend on the gate length, compared with devices with a silicon-nitride passivation layer, in both plastic and ceramic encapsulated devices. This paper describes characteristics of the shift, passivation, and packaging effects on the shift and modeling of the shift mechanism.