• DocumentCode
    1087028
  • Title

    Latchup prevention using an N-well epi-CMOS process

  • Author

    Holly, Patrick J. ; Akers, Lex A.

  • Author_Institution
    Motorola, Inc., Mesa, AZ
  • Volume
    30
  • Issue
    10
  • fYear
    1983
  • fDate
    10/1/1983 12:00:00 AM
  • Firstpage
    1403
  • Lastpage
    1405
  • Abstract
    A n-well epi-CMOS structure is described to reduce the latchup sensitivity of CMOS. Results demonstrate excellent latchup reduction.
  • Keywords
    Acoustical engineering; Anisotropic magnetoresistance; Conductivity; Electron devices; Latches; Metallization; Plasma applications; Plasma temperature; Substrates; Wet etching;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1983.21308
  • Filename
    1483209
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1087028