Design and implementation of a 3D-LSI image sensing processor

Author

Kioi, Kazumasa ; Shinozaki, Toshiyuki ; Toyoyama, Shinji ; Shirakawa, Kazuhiko ; Ohtake, Koui ; Tsuchimoto, Shuhei

Author_Institution

Sharp Corp., Nara, Japan

Volume

27

Issue

8

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

1130

Lastpage

1140

Abstract

A four-story structured image sensing processor implemented with three-dimensional LSI (3D-LSI) technology and integrating 5040 pixel photodiodes and 0.22 million transistors on a 14.3-mm² single die is described. The implemented chip allows a large degree of data parallelism in image computations where the image sensor unit operates without synchronous clocks. The chip, which is a second prototype, is able to sense 12 characters at the same time, and can recognize 64 different characters in upper and lower case, Arabic numerals, and some symbols, each consisting of a 10×14 matrix. The chip is made of a large number of simple processing elements working in parallel, which speeds up computation. The time needed to identify a sensed image as a memorized character is about 3 μs. Successful measurements of the principal functions verify the usefulness of the chip

Keywords

MOS integrated circuits; computerised pattern recognition; computerised picture processing; digital signal processing chips; image sensors; large scale integration; optical character recognition; parallel architectures; 3D-LSI image sensing processor; CMOS; NMOS; SOI transistors; data parallelism; image sensor unit; photodiodes; three-dimensional LSI technology; Character recognition; Clocks; Concurrent computing; Image sensors; Large scale integration; Parallel processing; Photodiodes; Pixel; Prototypes; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.148321

Filename

148321