Title :
Pipelining and bypassing in a VLIW processor
Author :
Abnous, Arthur ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
fDate :
6/1/1994 12:00:00 AM
Abstract :
This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor. The authors first describe the pipeline structure of their processor and analyze its performance and compare it to typical RISC-style pipeline structures given the context of a processor with multiple functional units. Next they study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time
Keywords :
parallel architectures; performance evaluation; pipeline processing; VLIW processor; bypassing; computer architecture; performance; pipeline data hazards; pipeline structure; very long instruction word; Computer architecture; Hardware; Hazards; Parallel processing; Performance analysis; Pipeline processing; Processor scheduling; Reduced instruction set computing; Registers; VLIW;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
