Title :
An offset reduction technique for use with CMOS integrated comparators and amplifiers
Author :
Atherton, James H. ; Simmonds, Thomas H.
Author_Institution :
Siemens Corporate Res. Inc., Princeton, NJ, USA
fDate :
8/1/1992 12:00:00 AM
Abstract :
Methods for reducing the input offset voltage of comparators and amplifiers are reviewed. A comparator that adjusts its own offset either at power-up or in response to a control input is presented. The nature of the offset adjustment is such that the comparator is capable of continuous-time operation. Room-temperature offset in the range of -100 to +100 μV are achievable. Adjusted offsets exhibit a temperature coefficient on the order of -1 μV/°C
Keywords :
CMOS integrated circuits; amplifiers; comparators (circuits); linear integrated circuits; -100 to 100 muV; CMOS integrated comparators; DAC; amplifiers; continuous-time operation; input offset voltage; offset reduction technique; Circuit stability; MOS integrated circuits; Manufacturing; Nonvolatile memory; Potentiometers; Resistors; Silicon; Temperature; Thin film circuits; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
