A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET´s

Author

Howes, Rupert ; Redman-White, William

Author_Institution

Dept. of Electron. & Comput. Sci., Southampton Univ., UK

Volume

27

Issue

8

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

1186

Lastpage

1193

Abstract

The frequency-dependent drain admittance of silicon-on-sapphire (SOS) MOSFETs is examined from the perspective of the circuit designer. Measurements of small-signal drain characteristics as a function of frequency, bias conditions, and device geometry, which have major implications for analog circuit design, are presented. These are explained in terms of a small-signal circuit model. Physical explanations for the observations are given and the poles and zeros of the model identified to assist designers carrying out hand calculations with easily manipulated expressions. Frequency-dependent thermal effects are discussed. It is shown that similar effects can be expected in other SOI technologies

Keywords

electric admittance; insulated gate field effect transistors; poles and zeros; semiconductor device models; thermal analysis; SOI technologies; SOS MOSFET; Si-Al₂O₃; analog circuit design; bias conditions; device geometry; floating-substrate; frequency-dependent drain admittance; poles and zeros; small-signal drain characteristics; small-signal model; thermal effects; Admittance; Analog circuits; Dielectric substrates; Fabrication; Frequency measurement; Geometry; Isolation technology; MOSFET circuits; Poles and zeros; Signal design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.148327

Filename

148327