DocumentCode
1087809
Title
A 1.5 V BiCMOS dynamic logic circuit using a “BiPMOS pull-down” structure for VLSI implementation of full adders
Author
Kuo, J.B. ; Chen, S.S. ; Chiang, C.S. ; Su, K.W. ; Lou, J.H.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
41
Issue
4
fYear
1994
fDate
4/1/1994 12:00:00 AM
Firstpage
329
Lastpage
332
Abstract
This paper presents a 1.5 V BiCMOS dynamic logic circuit using a “BiPMOS pull-down” structure, which is free from race problems, for VLSI implementation of full adders. Using the 1.5 V BiCMOS dynamic logic circuit, a 16-bit full adder circuit, which is composed of half adders and a carry look-ahead circuit, shows a 1.7 times improvement in speed as compared to the CMOS static one
Keywords
BiCMOS integrated circuits; VLSI; adders; carry logic; integrated logic circuits; 1.5 V; 16-bit adder; BiCMOS dynamic logic circuit; BiPMOS pull-down structure; VLSI implementation; carry look-ahead circuit; full adders; half adders; Adders; BiCMOS integrated circuits; CMOS logic circuits; Inverters; Logic circuits; Power supplies; Switches; Switching circuits; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher
ieee
ISSN
1057-7122
Type
jour
DOI
10.1109/81.285691
Filename
285691
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