Title :
FFT computation with systolic arrays, a new architecture
Author :
Boriakoff, Valentín
Author_Institution :
Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
fDate :
4/1/1994 12:00:00 AM
Abstract :
The use of the Cooley-Tukey algorithm for computing the 1-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; mathematics computing; matrix algebra; parallel algorithms; real-time systems; systolic arrays; 1024 point DFT; CMOS processor implementation; Cooley-Tukey algorithm; DSP chip; FFT computation; continuous real-time operation; decimation-in-frequency case; fixed point processor; linearly-connected arrays; matrix factorization; systolic architecture; systolic arrays; word-serial data input; CMOS process; Computer architecture; Computer simulation; Discrete Fourier transforms; Helium; Signal processing; Systolic arrays; Very large scale integration; Wires; Wiring;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on