Title :
On area/depth trade-off in LUT-based FPGA technology mapping
Author :
Cong, Jason ; Ding, Yuzheng
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
6/1/1994 12:00:00 AM
Abstract :
In this paper, we study the area and depth trade-off in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have developed a polynomial time optimal algorithm for computing an area-minimum mapping solution without node duplication for a K-bounded general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by most existing mapping algorithms in terms of both area and depth minimization.<>
Keywords :
Boolean functions; VLSI; application specific integrated circuits; approximation theory; logic CAD; logic arrays; polynomials; table lookup; K-bounded general Boolean network; LUT-based FPGA technology mapping; MCNC benchmark circuits; area minimization problem; area-minimizing mapping procedures; area/depth trade-off; depth relaxation operations; depth-optimal mapping; lookup-table; polynomial time optimal algorithm; Circuits; Design optimization; Field programmable gate arrays; Manufacturing; Minimization methods; Polynomials; Programmable logic arrays; Programmable logic devices; Table lookup; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
