Title :
PLA design for single-clock CMOS
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
8/1/1992 12:00:00 AM
Abstract :
The circuit implementation of a CMOS programmable logic array (PLA) is described for use with a single-phased clock, combining both dynamic and pseudo-NMOS design styles. Compact layout and high speed of operation is achieved with low static power dissipation. The circuit design, circuit speed, circuit layout, and timing diagram are presented
Keywords :
CMOS integrated circuits; logic arrays; logic design; PLA design; circuit layout; high speed; low static power dissipation; programmable logic array; single-clock CMOS; single-phased clock; CMOS logic circuits; CMOS technology; Clocks; Design automation; Inverters; Libraries; Logic functions; Phased arrays; Programmable logic arrays; Switches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
