Title :
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability
Author :
Liang, Xiaoyao ; Canal, Ramon ; Wei, Gu-Yeon ; Brooks, David
Author_Institution :
Harvard Univ., Cambridge
Abstract :
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.
Keywords :
DRAM chips; SRAM chips; cache storage; microprocessor chips; system-on-chip; transistors; 3-transistor, 1-diode DRAM; 6-transistor static memory structures; 6T SRAMs; L1 data cache; memory architecture; next-generation microprocessors; on-chip cache structures; process variability; Circuit stability; Degradation; Delay; Memory architecture; Microprocessors; Random access memory; Robust stability; Space technology; System-on-a-chip; Threshold voltage; caches; dynamic memory; process variation; variability;
Journal_Title :
Micro, IEEE
