DocumentCode
1088741
Title
An analytical model for the gate capacitance of small-geometry MOS structures
Author
Greeneich, Edwin W.
Author_Institution
Arizona State University, Tempe, AZ
Volume
30
Issue
12
fYear
1983
fDate
12/1/1983 12:00:00 AM
Firstpage
1838
Lastpage
1839
Abstract
An analytical formulation of the gate capacitance of MOS structures which takes into consideration the effects of electrode thickness and lateral gate dimensions is presented. Results are presented in normalized form covering a wide range of typical device dimensions.
Keywords
Analytical models; Conductors; Dielectric constant; Electrodes; MOS devices; Parasitic capacitance; Permittivity;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1983.21456
Filename
1483357
Link To Document